1. Field
The disclosed concept pertains generally to programmable logic apparatus and, more particularly, to such programmable logic apparatus for both vital and non-vital data. The disclosed concept also pertains to systems including such programmable logic apparatus.
2. Background Information
In vital railroad control systems, there is frequently the need to provide a human interface and a mechanism to communicate data to other control or monitoring systems. However, it must be clearly verifiable that non-vital functions cannot affect the vital operations of the system by either inadvertent code execution or excessive system loading. It is often difficult to prove the independency of the vital and non-vital functions running on a single processor. Therefore, it is advantageous to maintain complete autonomy between these two types of processing.
Ideally, non-vital functions would be executed independent of vital functions employing separate discrete processors with only limited data exchanged therebetween. However, the addition of another physical processor and supporting circuitry adds to the cost and size of the product.
Vital control systems using plural vital processors need a mechanism to output vital data (e.g., without limitation, a vital message including plural data bytes) for transmission over a serial communication network, channel, interface or media. Such vital processors need to be able to independently compose data content and authorize a single point of transmission of vital data (e.g., a vital message) only if all such vital processors agree on the data content.
In such a vital control system, there is the need that no one vital processor be able to serially transmit complete, valid vital data (e.g., a valid vital message).
U.S. Pat. No. 7,850,127 discloses a cab signal receiver demodulator employing redundant, diverse field programmable gate arrays. A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.
There is room for improvement in programmable logic apparatus.
There is also room for improvement in systems including programmable logic apparatus.